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MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3806 group is 8-bit microcomputer based on the 740 family core technology. The 3806 group is designed for controlling systems that require analog signal processing and include two serial I/O functions, A-D converters, and D-A converters. The various microcomputers in the 3806 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3806 group, refer to the section on group expansion.
* Clock generating circuit ....................... Internal feedback resistor
(connect to external ceramic resonator or quartz-crystal)
* Memory expansion possible
Specification Standard (unit) Minimum instruction execution time (s) Oscillation frequency (MHz) 0.5 8 Extended operating temperature version 0.5 8 4.0 to 5.5 32 -40 to 85 High-speed version 0.4 10 2.7 to 5.5 40 -20 to 85
FEATURES
* Basic machine-language instructions ....................................... 71 * Memory size * * * * * * *
ROM ................................................................ 12 K to 48 K bytes RAM ................................................................. 384 to 1024 bytes Programmable input/output ports ............................................. 72 Interrupts .................................................. 16 sources, 16 vectors Timers ............................................................................. 8 bit ! 4 Serial I/O1 .................... 8-bit ! 1 (UART or Clock-synchronized) Serial I/O2 .................................... 8-bit ! 1 (Clock-synchronized) A-D converter .................................................. 8-bit ! 8 channels D-A converter .................................................. 8-bit ! 2 channels
Power source voltage 3.0 to 5.5 (V) Power dissipation (mW) 32
Operating temperature -20 to 85 range (C)
APPLICATIONS
Office automation, VCRs, tuners, musical instruments, cameras, air conditioners, etc.
PIN CONFIGURATION (TOP VIEW)
P30 P31 P32/ONW P33/RESETOUT P34/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15
63 57 47 46 64 58 53 52 51 45 44 60 59 61 54 50 49 62 55 56 48 43 42 41
P87 P86 P85 P84 P83 P82 P81 P80 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63 /AN3
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
11 12 19 20 13 15 17 21 22 23 10 14 16 18 24 1 3 4 5 7 2 6 8 9
40 39 38 37 36 35 34 33
M38063M6-XXXFP
32 31 30 29 28 27 26 25
P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40 P41 RESET CNVSS P42/INT0
P62/AN2 P61/AN1 P60/AN0 P77 P76 P75 P74 P73/SRDY2 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/INT4 P52/INT3 P51/INT2 P50 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1
Package type : 80P6N-A 80-pin plastic-molded QFP
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
P32/ONW P33/RESETOUT P34/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13
57 45 43 52 50 46 42 51 60 58 55 56 49 48 47
P31 P30 P87 P86 P85 P84 P83 P82 P81 P80 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1
59
54
53
44
41
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 12 15 16 14 13 17 18 11 19 10 20
40 39 38 37 36 35 34 33 32
M38063M6-XXXGP M38063M6AXXXHP
31 30 29 28 27 26 25 24 23 22 21
P16/AD14 P17/AD15 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 Vss XOUT XIN P40 P41
RESET
CNVSS P42/INT0 P43/INT1 P44/RXD
1
4
2
5
6
7
3
Package type : 80P6S-A/80P6D-A 80-pin plastic-molded QFP
2
P60/AN0 P77 P76 P75 P74 P73/SRDY2 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/INT4 P52/INT3 P51/INT2 P50 P47/SRDY1 P46/SCLK1 P45/TXD
8
9
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N)
Reset input VSS VCC RESET
27 26 73 32
Clock input XIN CNVSS
Clock output XOUT
30
31
Data bus
Clock generating circuit
CPU
RAM ROM
X Prescaler 12 (8) Y S PC H PS CNTR0 CNTR1 PCL Prescaler Y (8) Prescaler X (8)
A
Timer 1 (8) Timer 2 (8)
Timer X (8)
Timer Y (8)
Serial I/O2 (8)
(8)
A-D converter D-A converter 2 (8) INT2 to INT4 D-A converter 1 (8)
Serial I/O1 (8)
INT0 to INT1
P8(8) P6(8) P5(8)
P7(8)
P4(8)
P3(8)
P2(8)
P1(8)
P0(8)
65 66 67 68 69 70 71 72 76 77 78 79 80 1 2 3
4 5 6 7 8 9 10 11 74 75
12 13 14 15 16 17 18 19
20 21 22 23 24 25 28 29
57 58 59 60 61 62 63 64
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
I/O port P8 I/O port P6
I/O port P7
I/O port P5
I/O port P4
I/O port P3
I/O port P2
I/O port P1
I/O port P0
VREF AVSS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3806 Group
3
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin VCC VSS CNVSS
Name Power source
Function Function except a port function * Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS. (Extended operating temperature version : 4.0 V to 5.5 V) (High-speed version : 2.7 V to 5.5 V) * This pin controls the operation mode of the chip. * Normally connected to VSS. * If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed. * Reference voltage input pin for A-D and D-A converters * GND input pin for A-D and D-A converters * Connect to VSS. * Reset input pin for active "L" * Input and output signals for the internal clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * * * * * * 8 bit CMOS I/O port I/O direction register allows each pin to be individually programmed as either input or output. At reset this port is set to input mode. In modes other than single-chip, these pins are used as address, data, and control bus I/O pins. CMOS compatible input level CMOS 3-state output structure
CNVSS
VREF AVSS
______
Analog reference voltage Analog power source Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4
RESET XIN XOUT P00 - P07 P10 - P17 P20 - P27 P30 - P37 P40, P41 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, _____ P47/SRDY1 P50 P51/INT2 - P53/INT4 P54/CNTR0, P55/CNTR1 P56/DA1, P57/DA2 P60/AN0 - P67/AN7
* 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * External interrupt input pin * Serial I/O1 I/O pins
I/O port P5
* 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * External interrupt input pin * Timer X and Timer Y I/O pins * D-A conversion output pins
I/O port P6
* 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure
* A-D conversion input pins
4
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (Continued)
Pin P70/SIN2, P71/SOUT2, P72/SCLK2, _____ P73/SRDY2 P74 - P77 P80 - P87 I/O port P8 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure Name I/O port P7 Function Function except a port function * 8-bit I/O port with the same function as port P0 * CMOS compatible input level * N-channel open-drain output structure * Serial I/O2 I/O pins
PART NUMBERING
Product M3806 3 M 6 - XXX FP Package type FP : 80P6N-A package GP : 80P6S-A package FS : 80D0 package ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character - : standard D : Extended operating temperature version A : High-speed version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes
5
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3806 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity ................................ 12 K to 48 K bytes RAM capacity .............................................. 384 to 1024 bytes
(2) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP 80P6S-A ........................... 0.65 mm-pitch plastic molded QFP 80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan
ROM size (bytes) 48K Mass product M38067MC/EC Mass product 32K M38067M8
28K Mass product 24K M38063M6/E6
20K Mass product 16K Mass product 12K M38062M3 M38062M4
8K
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Products under development : the development schedule and specification may be revised without notice.
Currently supported products are listed below Product name M38062M3-XXXFP M38062M3-XXXGP M38062M4-XXXFP M38062M4-XXXGP M38063M6-XXXFP M38063E6-XXXFP M38063E6FP M38063M6-XXXGP M38063E6-XXXGP M38063E6GP M38063E6FS M38067M8-XXXFP M38067M8-XXXGP M38067MC-XXXFP M38067EC-XXXFP M38067ECFP M38067MC-XXXGP M38067EC-XXXGP M38067ECGP (P) ROM size (bytes) ROM size for User in ( ) 12288 (12158) 16384 (16254) RAM size (bytes) 384 384 Package 80P6N-A 80P6S-A 80P6N-A 80P6S-A 80P6N-A 24576 (24446) 512 80P6S-A 80D0 80P6N-A 80P6S-A 80P6N-A 49152 (49022) 1024 80P6S-A Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version Mask ROM version One Time PROM version One Time PROM version EPROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version Mask ROM version One Time PROM version One Time PROM version
As of May 1996
(blank)
(blank)
32768 (32638)
1024
(blank)
(blank)
6
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
(EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3806 group (extended operating temperature version) as follows: (1) Support for mask ROM version ROM/PROM capacity ................................ 12 K to 48 K bytes RAM capacity .............................................. 384 to 1024 bytes
(2) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP
Memory Expansion Plan
ROM size (bytes) 48K
New product M38067ECD Mass product M38067MCD Mass product
32K
M38067M8D
28K Mass product 24K M38063M6D
20K Mass product 16K M38062M4D Mass product 12K M38062M3D
8K
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Currently supported products are listed below. Product name M38062M3DXXXFP M38062M4DXXXFP M38063M6DXXXFP M38067M8DXXXFP M38067MCDXXXFP M38067ECDXXXFP M38067ECDFP (P) ROM size (bytes) ROM size for User in ( ) 12288(12158) 16384(16254) 24576(24446) 32768(32638) 49152(49022) RAM size (bytes) 384 384 512 1024 1024 Package Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank)
As of May 1996
80P6N-A
7
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (HIGH-SPEED VERSION)
Mitsubishi plans to expand the 3806 group (high-speed version) as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity ................................ 24 K to 48 K bytes RAM capacity .............................................. 512 to 1024 bytes
(2) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP 80P6S-A ........................... 0.65 mm-pitch plastic molded QFP 80P6D-A ............................. 0.5 mm-pitch plastic molded QFP 80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan
ROM size (bytes) 48K New product M38067MCA/ECA New product 32K M38067M8A
28K New product 24K M38063M6A
20K
16K
12K
8K
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Products under development: the development schedule and specification may be revised without notice.
Currently supported products are listed below. Product name M38063M6AXXXFP M38063M6AXXXGP M38063M6AXXXHP M38067M8AXXXFP M38067M8AXXXGP M38067MCAXXXFP M38067ECAXXXFP M38067ECAFP M38067MCAXXXGP M38067ECAXXXGP M38067ECAGP M38067ECAFS (P) ROM size (bytes) ROM size for User in ( ) 24576 (24446) 32768 (32638) RAM size (bytes) Package 80P6N-A 80P6S-A 80P6D-A 80P6N-A 80P6S-A 80P6N-A 49152 (49022) 1024 80P6S-A 80D0 Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version
As of May 1996
512
1024
8
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 3806 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User's Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used.
CPU mode register
The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page
Not used (return "0" when read)
Fig. 1 Structure of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory Special function register (SFR) area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity (bytes) Address XXXX16
000016 SFR area 004016 010016 Zero page
192 256 384 512 640 768 896 1024
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16
RAM
XXXX16 Reserved area 044016
ROM area
ROM capacity (bytes) Address YYYY16 Address ZZZZ16
Not used YYYY16 Reserved ROM area
(128 bytes)
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ZZZZ16
ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page
Reserved ROM area
Fig. 2 Memory map diagram
10
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY)
AD/DA control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2)
Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON)
003816 003916 003A16 003B16 003C16 003D16 003E16
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2)
Serial I/O2 register (SIO2)
003F16
Fig. 3 Memory map of special function register (SFR)
11
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports Direction registers
The 3806 group has 72 programmable I/O pins arranged in nine I/O ports (ports P0 to P8). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin.
If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Pin P00 - P07
Name Port P0
Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits
P10 - P17
Port P1
P20 - P27
Port P2
P30 - P37 P40,P41 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, _____ P47/SRDY1 P50 P51/INT2, P52/INT3, P53/INT4 P54/CNTR0, P55/CNTR1 P56/DA1, P57/DA2 P60/AN0 - P67/AN7 P70/SIN2, P71/SOUT2, P72/SCLK2, _____ P73/SRDY2 P74 - P77 P80 - P87
Port P3
I/O Format CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level
Non-Port Function Address low-order byte output Address high-order byte output
Related SFRs CPU mode register
Ref.No.
CPU mode register (1)
Data bus I/O
CPU mode register
Control signal I/O
CPU mode register
Port P4
Input/output, individual bits
CMOS 3-state output CMOS compatible input level
External interrupt input
Interrupt edge selection register Serial I/O1 control register UART control register
(2) (3) (4) (5) (6) (1) (2)
Serial I/O1 function I/O
Port P5
Input/output, individual bits
CMOS 3-state output CMOS compatible input level
External interrupt input Timer X and Timer Y function I/O D-A conversion output
Interrupt edge selection register Timer XY mode register AD/DA control register
(7) (8)
Port P6
Input/output, individual bits
CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output CMOS compatible input level
A-D conversion input
(9) (10) (11) (12) (13) (14) (1)
Port P7
Input/output, individual bits
Serial I/O2 function I/O
Serial I/O2 control register
Port P8
Input/output, individual bits
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
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MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P1, P2, P3, P40, P41, P50, P8
Direction register
(2) Ports P42, P43, P51, P52, P53
Direction register
Data bus
Port latch
Data bus
Port latch
Interrupt input
(3) Port P44
Serial I/O1 enable bit Receive enable bit
Direction register
(4) Port P45
P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit
Direction register
Data bus
Port latch Data bus Port latch
Serial I/O1 input Serial I/O1output
(5) Port P46
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit
Direction register
(6) Port P47
Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O1 clock output
Serial I/O1 external clock input
Serial I/O1 ready output
(7) Ports P54, P55
Direction register
(8) Ports P56, P57
Direction register
Data bus
Port latch
Data bus
Port latch
Pulse output mode Timer output Counter input Interrupt input
D-A conversion output DA1 output enable bit (P56) DA2 output enable bit (P57)
Fig. 4 Port block diagram (single-chip mode) (1)
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MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P6
Direction register
(10) Port P70
Direction register
Data bus
Port latch
Data bus
Port latch
A-D conversion input Analog input pin selection bit
Serial I/O2 input
(11) Port P71
Serial I/O2 transmit completion signal Serial I/O2 port selection bit
(12) Port P72
Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit
Direction register Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 output
Serial I/O2 clock output
Serial I/O2 external clock input
(13) Port P73
(14) Ports P74 - Port P77
Direction register
SRDY2 output enable bit Data bus
Direction register
Port latch
Data bus
Port latch
Serial I/O2 ready output
Fig. 5 Port block diagram (single-chip mode) (2)
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MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by sixteen sources: seven external, eight internal, and one software.
Interrupt operation
When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
Notes on use
When the active edge of an external interrupt (INT0 to INT4, CNTR0, or CNTR1) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to "0". (4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 Serial I/O2 INT2 INT3 INT4 A-D converter BRK instruction Priority 1 2 3 4 Vector Addresses (Note 1) Low High FFFC16 FFFD16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O2 data transfer At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At completion of A-D conversion At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected
5 6 7 8 9 10 11 12 13 14 15 16 17
FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16
FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16
Valid when serial I/O1 is selected
STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable)
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
15
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 6 Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns "0" when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit Not used (returns "0" when read)
0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Serial I/O2 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD converter interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit
b7
b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Serial I/O2 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD converter interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 7 Structure of interrupt-related registers
16
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers
The 3806 group has four timers: timer X, timer Y, timer 1, and timer 2. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch.
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each be selected in one of four operating modes by setting the timer XY mode register. Timer Mode The timer counts f(XIN)/16 in timer mode. Pulse Output Mode Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge switch bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P54 ( or port P55) direction register to output mode. Event Counter Mode Operation in event counter mode is the same as in timer mode, except the timer counts signals input through the CNTR0 or CNTR1 pin. Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts at the oscillation frequency divided by 16 while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge switch bit is "1", the count continues during the time that the CNTR0 (or CNTR1) pin is at "L". In all of these modes, the count can be stopped by setting the timer X (timer Y) count stop bit to "1". Ever y time a timer underflows, the corresponding interrupt request bit is set.
b7
b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop
Fig. 8 Structure of timer XY register
17
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus Oscillator f(XIN) Divider 1/16 Pulse width measurement mode P54/CNTR0 pin CNTR0 active edge switch bit "0" "1" Timer mode Pulse output mode Prescaler X (8) Event counter mode CNTR0 active edge switch bit "1" "0" Q Timer X count stop bit To CNTR0 interrupt request bit Timer X (8) To timer X interrupt request bit Prescaler X latch (8) Timer X latch (8)
Q Toggle flip- flop R Timer X latch write pulse Pulse output mode Data bus T
Port P54 direction register
Port P54 latch Pulse output mode
Prescaler Y latch (8) Pulse width measurement mode P55/CNTR1 pin CNTR1 active edge switch bit "0" "1" Timer mode Pulse output mode Prescaler Y (8) Event counter mode CNTR1 active edge switch bit "1" "0" Q Timer Y count stop bit
Timer Y latch (8)
Timer Y (8)
To timer Y interrupt request bit To CNTR1 interrupt request bit
Q Toggle flip- flop R Timer Y latch write pulse Pulse output mode T
Port P55 direction register
Port P55 latch Pulse output mode
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit
To timer 1 interrupt request bit
Fig. 9 Block diagram of timer X, timer Y, timer 1, and timer 2
18
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
Clock synchronous serial I/O mode
Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816).
Data bus Serial I/O1 control register Address 001A16
Address 001816 Receive buffer P44/RXD Receive shift register Shift clock P46/SCLK1
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
f(XIN) XIN
BRG count source selection bit 1/4
Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4
P47/SRDY1
F/F
Falling-edge detector Shift clock
Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
P45/TXD
Transmit shift register Transmit buffer Address 001816 Data bus
Fig. 10 Block diagram of clock synchronous serial I/O1
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write pulse to receive/transmit buffer (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 11 Operation of clock synchronous serial I/O1 function
19
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous serial I/O (UART) mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received.
Data bus Address 001816 Receive buffer OE Character length selection bit P44/RXD STdetector 7 bits 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Receive shift register 1/16 UART control register Address 001B16 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI)
f(XIN)
Fig. 12 Block diagram of UART serial I/O
20
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1V
Serial output TXD
ST
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
V
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 13 Operation of UART serial I/O function
Serial I/O1 control register (SIO1CON) 001A16
The serial I/O control register consists of eight control bits for the serial I/O function.
UART control register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin.
spectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
Transmit buffer/Receive buffer register (TB/ RB) 001816
The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
Serial I/O1 status register (SIO1STS) 001916
The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-
Baud rate generator (BRG) 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
21
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 status register (SIO1STS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as S RDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44 to P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44 to P47 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
Fig. 14 Structure of serial I/O control registers
22
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register.
b7
b0
Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits
b2 b1 b0
Serial I/O2 control register (SIO2CON) 001D16
The serial I/O2 control register contains seven bits which control various serial I/O functions.
0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock Not used (returns "0" when read)
Fig. 15 Structure of serial I/O2 control register
1/8 1/16 Divider 1/32 1/64 1/128 1/256
Internal synchronous clock selection bits
Data bus
XIN
P73 latch "0" Serial I/O2 synchronous clock selection bit SRDY2 Synchronization circuit SCLK2
"1" "0"
P73/SRDY2
"1" SRDY2 output enable bit
External clock
P72 latch "0"
P72/SCLK2
"1" Serial I/O2 port selection bit P71 latch "0"
Serial I/O counter 2 (3)
Serial I/O2 interrupt request
P71/SOUT2
"1" Serial I/O2 port selection bit
P70/SIN2
Serial I/O shift register 2 (8)
Fig. 16 Block diagram of serial I/O2 function
23
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1) Serial I/O2 register write signal
(Note 2)
Serial I/O2 output SOUT2 Serial I/O2 input SIN2
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion.
Fig. 17 Timing of serial I/O2 function
24
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
The functional blocks of the A-D converter are described below.
[Comparator and Control circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that the comparator is constructed linked to a capacitor, so set f(XIN) to 500 kHz or more during an A-D conversion.
[A-D conversion register]
The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read.
[AD/DA control register]
The AD/DA control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion. Bits 6 and 7 are used to control the output of the D-A converter.
b7 b0
AD/DA control register (ADCON : address 003416) Analog input pin selection bits
b2 b1 b0
[Comparison voltage generator]
The comparison voltage generator divides the voltage between AVSS and VREF into 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of the ports P60/AN0 to P67/AN7, and inputs the voltage to the comparator.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: P60/AN0 1: P61/AN1 0: P62/AN2 1: P63/AN3 0: P64/AN4 1: P65/AN5 0: P66/AN6 1: P67/AN7
AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (return "0" When read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled
Fig.18 Structure of AD/DA control register
Data bus
AD/DA control register (Address 0034 16)
b7
b0
3 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 A-D control circuit A-D interrupt request
Channel selector
Comparator
A-D conversion register (Address 0035 16) 8 Resistor ladder
VREF AVSS
Fig. 19 Block diagram of A-D converter
25
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A Converter
The 3806 group has two internal D-A converters (DA1 and DA2) with 8-bit resolutions. The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from the DA1 or DA2 pin by setting the DA output enable bit to "1". When using the D-A converter, the corresponding port direction register bit (DA1/P56 or DA2/P57) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V = VREF ! n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DA output enable bits are cleared to "0", and the P56/DA1 and P57/ DA2 pins are set to input (high impedance). The D-A output is not buffered, so connect an external buffer when driving a low-impedance load. Set VCC to 4.0 V or more when using the D-A converter.
D-A1 conversion register (8) DA1 output enable bit P56/DA1
Data bus
R-2R resistor ladder
D-A2 conversion register (8) DA2 output enable bit P57/DA2
R-2R resistor ladder
Fig. 20 Block diagram of D-A converter
"0" DA1 output enable bit R
R 2R
R 2R
R 2R
R 2R
R 2R
R 2R
2R 2R LSB
P56/DA1
"1" MSB
2R
D-A1 conversion register AVSS VREF
"0"
"1"
Fig. 21 Equivalent connection circuit of D-A converter
26
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
______
To reset the microcomputer, the RESET pin should be held at an ______ "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (Note 1), reset is released. Internal operation does not begin until after 8 to 13 XIN clock cycles are completed. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.8 V for VCC of 4.0 V (Note 2). Note 1. The power source voltage should be between the following voltage. * Between 3.0 V and 5.5 V for standard version * Between 4.0 V and 5.5 V for extended operating temperature version * Between 2.7 V and 5.5 V for high-speed version Note 2. Reset input voltage is less than the following voltage. * 0.6 V for VCC = 3.0 V * 0.8 V for VCC = 4.0 V * 0.54 V for VCC = 2.7 V
Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) Port P5 direction register (7) Port P6 direction register (8) Port P7 direction register (9) Port P8 direction register (10) Serial I/O1 status register (11) Serial I/O1 control register (12) UART control register (13) Serial I/O2 control register (14) Prescaler 12 (15) Timer 1 (16) Timer 2 (000116) * * * (000316) * * * (000516) * * * (000716) * * * (000916) * * * (000B16) * * * (000D16) * * * (000F16) * * * (001116) * * *
Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016
(001916) * * * 1 0 0 0 0 0 0 0 (001A16) * * * 0016
(001B16) * * * 1 1 1 0 0 0 0 0 (001D16) * * * (002016) * * * (002116) * * * (002216) * * * (002316) * * * (002416) * * * (002516) * * * (002616) * * * (002716) * * * 0016 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16
4.0V Power source 0V voltage 0.8V
(17) Timer XY mode register (18) Prescaler X (19) Timer X (20) Prescaler Y
Reset input 0V voltage
(21) Timer Y (22) AD/DA control register (23) D-A1 conversion register
(003416) * * * 0 0 0 0 1 0 0 0 (003616) * * * (003716) * * * 0016 0016 0016
1 5 M51953AL 4 0.1 F
VCC RESET
(24) D-A2 conversion register
(25) Interrupt edge selection register (003A16) * * * (26) CPU mode register (27) Interrupt request register 1 (28) Interrupt request register 2
(003B16) * * * 0 0 0 0 0 0 V 0 (003C16) * * * (003D16) * * * (003E16) * * * (003F16) * * * 0016 0016 0016 0016
3
VSS 3806 group
(29) Interrupt control register 1 (30) Interrupt control register 2 (31) Processor status register
(PS) ! ! ! ! ! 1 ! ! (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16
Fig. 22 Example of reset circuit
(32) Program counter
Note. ! : Undefined V : The initial values of CM1 are determined by the level at the CNVSS pin. The contents of all other registers and RAM are undefined after a reset, so they must be initialized by software.
Fig. 23 Internal status of microcomputer after reset
27
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN
RESET
RESETOUT (internal reset) SYNC
Address
?
?
?
?
?
FFFC
FFFD
ADH, ADL
Reset address from the vector table
Data XIN: 8 to 13 clock cycles
?
?
?
?
?
ADL
ADH
Notes 1: f(XIN) and f() are in the relationship: f(XIN)=2 * f(). 2: A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 24 Timing of reset
28
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open.
When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed.
Oscillation control
Stop Mode If the STP instruction is executed, the internal clock stops at an "H". Timer 1 is set to "0116" and prescaler 12 is set to "FF16". Oscillator restarts when an external interrupt is received, but the internal clock remains at an "H" until timer 1 underflow. This allows time for the clock circuit oscillation to stabilize. If oscillator is restarted by a reset, no wait time is generated, so ______ keep the RESET pin at an "L" level until oscillation has stabilized. Wait Mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator itself does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed.
XIN
XOUT
CIN
COUT
Fig. 25 Ceramic resonator circuit
XIN
XOUT Open
External oscillation circuit
Vcc Vss
Fig. 26 External clock input circuit
Interrupt request
Interrupt disable flag (I) Reset STP instruction
S
Q
S
Q
Q
S
Reset
R
WIT instruction
R
R
STP instruction
output
ONW pin Single-chip mode 1/2 Rd
Internal clock ONW control 1/8 Prescaler 12 FF16 0116 Timer 1
Reset or STP instruction
Rf XIN XOUT
Fig. 27 Block diagram of clock generating circuit
29
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Processor Modes
Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits CM0 and CM1 (bits 0 and 1 of address 003B16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table 2. Functions of ports in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs low-order byte of address. Port P1 Outputs high-order byte of address. Operates as I/O pins for data D7 to D0 Port P2 (including instruction codes). P30 and P31 function only as output pins (except that the port latch cannot be read). _____ P32 is the ONW input pin.
_________
000016 000816 004016
SFR area Internal RAM reserved area
000016 000816 004016
SFR area Internal RAM reserved area
044016
V
044016
YYYY16 FFFF16
Internal ROM
FFFF16
Microprocessor mode The shaded areas are external memory areas.
V : YYYY16 is the start address of internal ROM.
Memory expansion mode
Port P3
P33 is the RESETOUT output pin. (Note) P34 is the output pin. P35 is the SYNC output pin. ___ P36 is the WR output pin, and P37 is the ___ RD output pin.
Fig. 28 Memory maps in various processor modes
b7
b0
Note: If CNVSS is connected to VSS, the microcomputer goes to single-chip mode after a reset, so this pin cannot be used _________ as the RESETOUT output pin. Single-Chip Mode Select this mode by resetting the microcomputer with CNVSS connected to VSS. Memory Expansion Mode Select this mode by setting the processor mode bits to "01" in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. Internal ROM will take precedence over external memory if addresses conflict. Microprocessor Mode Select this mode by resetting the microcomputer with CNVSS connected to VCC, or by setting the processor mode bits to "10" in software with CNVSS connected to VSS. In microprocessor mode, the internal ROM is no longer valid and external memory must be used.
CPU mode register (CPUM : address 003B16) Processor mode bits
b1 b0
0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return "0" when read)
Fig. 29 Structure of CPU mode register
30
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bus control with memory expansion
_____
The 3806 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. _____ If an "L" level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle ___ is extended by one cycle of . During this extended period, the RD or ___ WR signal remains at "L". This extension period is valid only for writing to and reading from addresses 000016 to 000716 and 044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in memory expansion mode, and only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
AD15 to AD0 RD WR ONW V V V
V : Period during which ONW input signal is received During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal is received.
_____
Fig. 30 ONW function timing
31
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex_____ ternal clock and it is to output the SRDY1 _____ set the transmit signal, enable bit, the receive enable bit, and the SRDY1 output enable bit to "1". Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conver____ sion. (If the ONW pin has been set to "L", the A-D conversion will take twice as long to match the longer bus cycle, and so f(XIN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conversion.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC.
D-A Converter
The accuracy of the D-A converter becomes poor rapidly under the VCC = 4.0 V or less condition.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency. _____ When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock may be one fourth the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register.
Memory Expansion Mode and Microprocessor Mode
Execute the LDM or STA instruction for writing to port P3 (address 000616) in memory expansion mode and microprocessor mode. Set areas which can be read out and write to port P3 (address 000616) in a memory, using the read-modify-write instruction (SEB, CLB).
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers.
32
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area.
Package 80P6N-A 80P6S-A 80D0
Name of Programming Adapter PCA4738F-80A PCA4738G-80A PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 40 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 31 Programming and testing of One Time PROM version
33
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P30-P37, P40-P47, P60-P67, P70-P77, VREF ______ Input voltage RESET, XIN Input voltage CNVSS Output voltage P00-P07, P10-P17, P30-P37, P40-P47, P60-P67, P70-P77, XOUT Power dissipation Operating temperature Storage temperature P20-P27, P50-P57, P80-P87, All voltages are based on VSS. Output transistors are cut off. P20-P27, P50-P57, P80-P87, Ta = 25 C Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 500 -20 to 85 -40 to 125 Unit V V V V V mW C C
RECOMMENDED OPERATING CONDITIONS (Vcc=3.0 to 5.5v, Ta=-20 to 85C,unless otherwise noted)
Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Parameter Power source voltage (f(XIN) < 2 MHz) (Note 1) Power source voltage (f(XIN) = 8 MHz) (Note 1) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ "H" input voltage RESET, XIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ "L" input voltage RESET "L" input voltage XIN "L" input voltage CNVSS "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 2) "H" total peak output current P40-P47,P50-P57, P60-P67 (Note 2) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 2) "L" total peak output current P40-P47,P50-P57, P60-P67, P70-P77 (Note 2) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 2) "H" total average output current P40-P47,P50-P57, P60-P67 (Note 2) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 2) "L" total average output current P40-P47,P50-P57, P60-P67, P70-P77 (Note 2) "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 3) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 (Note 3) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 4) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 (Note 4) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) Internal clock oscillation frequency (VCC = 3.0 to 4.0 V)
6
Limits Min. 3.0 4.0 2.0 3.0 0 AVSS 0.8 VCC 0.8 VCC 0 0 0 0 VCC VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC 0.2 VCC -80 -80 80 80 -40 -40 40 40 -10 10 -5 5 Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC VCC
Unit V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA
8 MHz 6 VCC-16
Note 1: The minimum power source voltage is X + 16 [V] (f(XIN) = XMHz) on the condition of 2 MHz < f(XIN) < 8 MHz. 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 3: The peak output current is the peak current flowing in each port. 4: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
34
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Symbol Parameter
(VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions IOH = -10 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 3.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 3.0 to 5.5 V Min. VCC-2.0 V VCC-1.0 2.0 V 1.0 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz, VCC = 5 V f(XIN) = 5 MHz, VCC = 5 V f(XIN) = 2 MHz, VCC = 3 V When WIT instruction is executed with f(Xin) = 8MHz,Vcc=5V When WIT instruction is executed with f(Xin) = 5MHz,Vcc=5V When WIT instruction is executed with f(Xin) = 2MHz,Vcc=3V When STP instruction Ta = 25 C is executed with clock (Note 2) stopped, output Ta = 85 C transistors isolated. (Note 2) 5.0 5.0 4 -5.0 -5.0 -4 2.0 6.4 4 0.8 1.5 1 0.2 0.1 1 A 10 5.5 13 8 2.0 V V V A A A A A A V Limits Typ. Max. Unit
VOH
"H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67, P70-P77, P80-P87 Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0-INT4 RXD, SCLK1, SIN2, SCLK2 ______ RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ RESET, CNVSS XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ RESET, CNVSS XIN
VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL IIL VRAM
"H" input current "H" input current "L" input current
"L" input current "L" input current RAM hold voltage
mA
ICC
Power source current
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
A-D CONVERTER CHARACTERISTICS
Symbol -- -- tCONV RLADDER IVREF II(AD) Parameter
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -20 to 85 C, unless otherwise noted) Test conditions Min. Limits Max. Typ. 8 1 2.5 50 35 150 200 0.5 5.0 Unit Bits LSB tC() k A A
Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current
VREF = 5.0 V
50
Note: When D-A conversion registers (addresses 003616 and 003716) contain "0016".
35
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER CHARACTERISTICS
Symbol -- -- tsu RO IVREF Resolution Absolute accuracy Parameter
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = -20 to 85 C, unless otherwise noted) Test conditions Min. Limits Typ. Max. 8 1.0 2.5 3 4 3.2 Unit Bits % s k mA
VCC = 4.0 to 5.5 V VCC = 3.0 to 4.0 V 1 2.5
Setting time Output resistor Reference power source input current (Note)
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016", and excluding currents flowing through the A-D resistance ladder.
36
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2)
_____
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time
Min. 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200
Limits Typ.
Max.
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: When bit 6 of address 001A16 is "1". Divide this value by four when bit 6 of address 001A16 is "0".
TIMING REQUIREMENTS 2 (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2)
_____
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time
Min. 2 500/ (3 VCC-8) 200/ (3 VCC-8) 200/ (3 VCC-8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300
Limits Typ.
Max.
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When bit 6 of address 001A16 is "1". Divide this value by four when bit 6 of address 001A16 is "0".
37
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Test conditions Min. tc(SCLK1)/2-30 tc(SCLK1)/2-30 -30 30 30 tc(SCLK2)/2-160 tc(SCLK2)/2-160 Fig. 33 0 10 10 40 30 30 200 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig. 32
140
Fig. 32
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: Pins XOUT and P70-P77 are excluded.
SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Test conditions Limits Min. tc(SCLK1)/2-50 tc(SCLK1)/2-50 -30 50 50 tc(SCLK2)/2-240 tc(SCLK2)/2-240 Fig. 33 0 20 20 50 50 50 400 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig. 32
350
Fig. 32
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: Pins XOUT and P70-P77 are excluded.
38
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
Symbol tsu(ONW-) ____ th(-ONW) tsu(DB-) th(-DB) ____ __ tsu(ONW-RD) ____ ___ tsu(ONW-WR) __ ____ th(RD-ONW) ___ ____ th(WR-ONW) __ tsu(DB-RD) __ th(RD-DB)
____
Before ONW input set up time _____ After ONW input hold time Before data bus set up time After data bus hold time ___ _____ Before RD ONW input set up time ___ _____ Before WR ONW input set up time ___ _____ After RD ONW input hold time ___ _____ After WR ONW input hold time ___ Before RD data bus set up time ___ After RD data bus hold time
_____
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Parameter Unit Min. Typ. Max. ns -20 ns -20 ns 60 ns 0 -20 -20 65 0 ns ns ns ns
SWITCHING CHARACTERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tc() Parameter Test conditions Min. tc(XIN)-10 tc(XIN)-10 6 6 20 10 25 10 20 10 10 5 20 40 45 Limits Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)-15 tc(XIN)-20 5 5 15 10 0 200 200 65 ns ns ns ns ns ns ns ns
clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time SYNC valid time ___ ___ RD and WR delay time ___ ___ RD and WR valid time After data bus delay time After data bus valid time ___ ___ RD pulse width, WR pulse width __ ___ ___ twL(RD) ___ RD pulse width, WR pulse width twL(WR) (When one-wait is valid) ___ __ td(AH-RD) After AD15-AD8 ___ delay time RD ___ td(AH-WR) After AD15-AD8 WR delay time ___ __ td(AL-RD) After AD7-AD0 ___ delay time RD ___ td(AL-WR) After AD7-AD0 WR delay time ___ __ tv(RD-AH) After ___ AD15-AD8 valid time RD ___ tv(WR-AH) After WR AD15-AD8 valid time ___ __ tv(RD-AL) After ___ AD7-AD0 valid time RD ___ tv(WR-AL) After WR AD7-AD0 valid time ___ ___ td(WR-DB) After WR data bus delay time ___ ___ tv(WR-DB) After WR data bus valid time _________ ___ _____ td(RESET-RESETOUT) RESETOUT output delay time (Note 1) _________ _____ tv(-RESET) RESETOUT output valid time (Note 1) twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) ___ td(-WR) ___ tv(-WR) td(-DB) tv(-DB)
__________
3 15 tc(XIN)-10 3tc(XIN)-10 tc(XIN)-35 tc(XIN)-40 0 0
20 10 70
Fig. 32
Note 1: The______ RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
39
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
Symbol tsu(ONW-) ____ th(-ONW) tsu(DB-) th(-DB) ____ __ tsu(ONW-RD) ____ ___ tsu(ONW-WR) __ ____ th(RD-ONW) ___ ____ th(WR-ONW) __ tsu(DB-RD) __ th(RD-DB)
____
(VCC = 3.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Min. -20 -20 180 0 -20 -20 185 0 Limits Typ. Unit Max. ns ns ns ns ns ns ns ns
Parameter Before ONW input set up time _____ After ONW input hold time Before data bus set up time After data bus hold time ___ _____ Before RD ONW input set up time ___ _____ Before WR ONW input set up time ___ _____ After RD ONW input hold time ___ _____ After WR ONW input hold time ___ Before RD data bus set up time ___ After RD data bus hold time
_____
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
Symbol tc() twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) ___ td(-WR) ___ tv(-WR) td(-DB) tv(-DB) twL(RD) ___ twL(WR) td(AH-RD) ___ td(AH-WR) __ td(AL-RD) ___ td(AL-WR) __ tv(RD-AH) ___ tv(WR-AH) __ tv(RD-AL) ___ tv(WR-AL) ___ td(WR-DB) ___ tv(WR-DB) ___ _____ td(RESET-RESETOUT) _____ tv(-RESET)
__ __
(VCC = 3.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions Min. Limits Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 ns ns ns ns ns ns after
Parameter clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time SYNC valid time
___ ___ ___ ___
tc(XIN)-20 tc(XIN)-20 150 10 10 15 150 15 40 20 15 7
RD and WR delay time RD and WR valid time After data bus delay time After data bus valid time
___ ___ ___
3 15 tc(XIN)-20 3tc(XIN)-20 tc(XIN)-145 tc(XIN)-145 5 5
25 15 200
RD pulse width, WR pulse width ___ RD pulse width, WR pulse width (when one-wait is valid)
___
Fig. 32
After AD15-AD8 ___ delay time RD After AD15-AD8 WR delay time ___ After AD7-AD0 ___ delay time RD After AD7-AD0 WR delay time ___ After ___ AD15-AD8 valid time RD After WR AD15-AD8 valid time ___ After ___ AD7-AD0 valid time RD After WR AD7-AD0 valid time
___
195 After WR data bus delay time ___ 10 After WR data bus valid time _________ RESETOUT output delay time (Note 1) 300 _________ 0 300 RESETOUT output valid time (Note 1) __________ Note1: The______ RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles the RESET input goes "H".
40
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS (Extended operating temperature version)
Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P30-P37, P40-P47, P60-P67, P70-P77, VREF ______ Input voltage RESET, XIN Input voltage CNVSS Output voltage P00-P07, P10-P17, P30-P37, P40-P47, P60-P67, P70-P77, XOUT Power dissipation Operating temperature Storage temperature Conditions P20-P27, P50-P57, P80-P87, All voltage are based on VSS. Output transistors are cut off. P20-P27, P50-P57, P80-P87, Ta = 25 C Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 500 -40 to 85 -65 to 150 Unit V V V V V mW C C
RECOMMENDED OPERATING CONDITIONS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Parameter Power source voltage Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ "H" input voltage RESET, XIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "H" total peak output current P40-P47,P50-P57, P60-P67 (Note 1) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "L" total peak output current P40-P47,P50-P57, P60-P67, P70-P77 (Note 1) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "H" total average output current P40-P47,P50-P57, P60-P67 (Note 1) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "L" total average output current P40-P47,P50-P57, P60-P67, P70-P77 (Note 1) "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 2) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 (Note 2) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 3) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 (Note 3) Internal clock oscillation frequency Min. 4.0 2.0 4.0 0 AVSS 0.8 VCC 0.8 VCC 0 0 0 VCC VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC -80 -80 80 80 -40 -40 40 40 -10 10 -5 5 8 Limits Typ. 5.0 0 Max. 5.5 VCC VCC Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
41
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67, P70-P77, P80-P87 Hysteresis CNTR0, CNTR1, INT0-INT4 Hysteresis RXD, SCLK1, SIN2, SCLK2 ______ Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ "L" input current RESET, CNVSS "L" input current XIN RAM hold voltage Test conditions IOH = -10 mA Min. VCC-2.0 Limits Typ. Max. Unit V
VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL IIL VRAM
IOL = 10 mA 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz f(XIN) = 5 MHz When WIT instruction is executed with f(XIN) = 8 MHz When WIT instruction is executed with f(XIN) = 5 MHz When STP instruction Ta = 25 C is executed with clock (Note 2) stopped, output Ta = 85 C transistors isolated. (Note 2)
2.0
V V V V
5.0 5.0 4 -5.0 -5.0 -4 2.0 6.4 4 1.5 1 0.1 1 5.5 13 8
A A A A A A V
mA
ICC
Power source current
A 10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
A-D CONVERTER CHARACTERISTICS(Extended operating temperature version)
Symbol -- -- tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current Test conditions
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -40 to 85 C, unless otherwise noted) Min. Limits Typ. 1 35 150 0.5 Max. 8 2.5 50 200 5.0 Unit Bits LSB tC() k A A
VREF = 5.0 V
50
Note: When D-A conversion registers (addresses 003616 and 003716) contain "0016".
42
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER CHARACTERISTICS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = -40 to 85 C, unless otherwise noted) Symbol -- -- tsu RO IVREF Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) Test conditions Limits Typ. Unit Bits % s k mA
Min.
1
2.5
Max. 8 1.0 3 4 3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016", and excluding currents flowing through the A-D resistance ladder.
43
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (Extended operating temperature version)
Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2)
_____
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Min. 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is "1". Divide this value by four when bit 6 of address 001A16 is "0".
SWITCHING CHARACTERISTICS (Extended operating temperature version)
Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rise time Serial I/O1 clock output fall time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output fall time CMOS output rise time (Note 2) CMOS output fall time (Note 2) Test conditions
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Min. tc(SCLK1)/2-30 tc(SCLK1)/2-30 -30 30 30 tc(SCLK2)/2-160 tc(SCLK2)/2-160 Fig. 33 0 10 10 40 30 30 200 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig. 32
140
Fig. 32
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: Pins XOUT pin and P70-P77 are excluded.
44
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted)
Symbol tsu(ONW-) ____ th(-ONW) tsu(DB-) th(-DB) ____ __ tsu(ONW-RD) ____ ___ tsu(ONW-WR) __ ____ th(RD-ONW) ___ ____ th(WR-ONW) __ tsu(DB-RD) __ th(RD-DB)
____
Parameter Before ONW input set up time _____ After ONW input hold time Before data bus set up time After data bus hold time ___ _____ Before RD ONW input set up time ___ _____ Before WR ONW input set up time ___ _____ After RD ONW input hold time ___ _____ After WR ONW input hold time ___ Before RD data bus set up time ___ After RD data bus hold time
_____
Min. -20 -20 60 0 -20 -20 65 0
Limits Typ.
Max.
Unit ns ns ns ns ns ns ns ns
SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted)
Symbol tc() Parameter Test conditions Min. tc(XIN)-10 tc(XIN)-10 6 6 20 10 25 10 20 10 10 5 20 40 45 Limits Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)-15 tc(XIN)-20 5 5 15 10 0 200 200 65 ns ns ns ns ns ns ns ns
clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time SYNC valid time ___ ___ RD and WR delay time ___ ___ RD and WR valid time After data bus delay time After data bus valid time ___ ___ __ RD pulse width, WR pulse width ___ ___ twL(RD) __ RD pulse width, WR pulse width twL(WR) (When one-wait is valid) ___ __ td(AH-RD) After AD15-AD8 ___ delay time RD ___ td(AH-WR) After AD15-AD8 WR delay time ___ __ td(AL-RD) After AD7-AD0 ___ delay time RD ___ td(AL-WR) After AD7-AD0 WR delay time ___ __ tv(RD-AH) After ___ AD15-AD8 valid time RD ___ tv(WR-AH) After WR AD15-AD8 valid time ___ __ tv(RD-AL) After ___ AD7-AD0 valid time RD ___ tv(WR-AL) After WR AD7-AD0 valid time ___ ___ td(WR-DB) After WR data bus delay time ___ ___ tv(WR-DB) After WR data bus valid time _________ ___ _____ td(RESET-RESETOUT) RESETOUT output delay time (Note 1) _________ _____ tv(-RESET) RESETOUT output valid time (Note 1) twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) ___ td(-WR) ___ tv(-WR) td(-DB) tv(-DB)
_________
3 15 tc(XIN)-10 3tc(XIN)-10 tc(XIN)-35 tc(XIN)-40 0 0
20 10 70
Fig. 32
Note 1: The______ RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
45
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS (High-speed version)
Symbol VCC VI VI VI Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, VREF, XIN ______ Input voltage RESET Mask ROM version Input voltage CNVSS PROM version Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 13 -0.3 to VCC +0.3 Ta = 25 C 500 -20 to 85 -40 to 125 Unit V V V V
All voltages are based on VSS. Output transistors are cut off.
VO Pd Topr Tstg
V mW C C
RECOMMENDED OPERATING CONDITIONS (High-speed version)
(VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA VIH VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Parameter Min. 2.7 4.0 Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC VCC 0 VCC VCC 0.2 VCC 0.16 VCC -80 -80 80 80 -40 -40 40 40 -10 10 -5 5 10 4.5VCC-8 Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz
Power source voltage (f(XIN) < 4.15 MHz) Power source voltage (f(XIN) = 10 MHz) Power source voltage Analog reference voltage (when A-D converter is used) 2.0 Analog reference voltage (when D-A converter is used) 2.7 Analog power source voltage Analog input voltage AN0-AN7 AVSS "H" input voltage P00-P07, P10-P17, P20-P27, P30-P37, ______ P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, RESET, XIN, 0.8 VCC CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, ______ 0 P50-P57, P60-P67, P70-P77, P80-P87, RESET, CNVSS "L" input voltage XIN 0 "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "H" total peak output current P40-P47,P50-P57, P60-P67 (Note 1) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "L" total peak output current P40-P47,P50-P57, P60-P67, P70-P77 (Note 1) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "H" total average output current P40-P47,P50-P57, P60-P67 (Note 1) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 (Note 1) "L" total average output current P40-P47,P50-P57, P60-P67, P70-P77 (Note 1) "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 2) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 (Note 2) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 3) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 (Note 3) Internal clock oscillation frequency (4.0 V < VCC < 5.5 V) Internal clock oscillation frequency (2.7 V < VCC < 4.0 V)
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
46
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67, P70-P77, P80-P87 Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0-INT4 RXD, SCLK1, SIN2, SCLK2 ______ RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 ______ RESET, CNVSS XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, ______ RESET, CNVSS XIN Test conditions IOH = -10 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.7 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.7 to 5.5 V Min. VCC-2.0 V VCC-1.0 2.0 V 1.0 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS With clock stopped f(XIN) = 10 MHz, VCC = 5 V f(XIN) = 4 MHz, VCC = 2.7 V When WIT instruction is executed with f(XIN) = 10 MHz, VCC = 5 V When WIT instruction is executed with f(XIN) = 4 MHz, VCC = 2.7 V When STP instruction Ta = 25 C is executed with clock (Note 2) stopped, output Ta = 85 C transistors isolated. (Note 2) -4 2.0 8 1.3 2 0.3 0.1 1 A 10 5.5 16 2 5.0 5.0 4 -5.0 V V V A A A A A V Limits Typ. Max. Unit
VOH
VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL VRAM
"H" input current "H" input current "L" input current
"L" input current RAM hold voltage
mA
ICC
Power source current
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
A-D CONVERTER CHARACTERISTICS (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current Test conditions Limits Typ. 1 35 150 0.5 Unit Bits LSB tC() k A A
Min.
Max. 8 2.5 50 200 5.0
VREF = 5.0 V
50
Note: When D-A conversion registers (addresses 003616 and 003716) contain "0016".
47
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER CHARACTERISTICS (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.7 V to VCC, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- tsu RO IVREF Resolution Absolute accuracy VCC = 4.0 to 5.5 V VCC = 2.7 to 5.5 V 1 2.5 Parameter Test conditions Min. Limits Typ. Max. 8 1.0 2.5 3 4 3.2 Unit Bits % s k mA
Setting time Output resistor Reference power source input current (Note)
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016", and excluding currents flowing through the A-D resistance ladder.
48
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2)
_____
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time
Min. 2 100 40 40 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200
Limits Typ.
Max.
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1". Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0".
TIMING REQUIREMENTS 2 (High-speed version)
VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2)
_____
Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time
Min. 2 1000/ (4.5 VCC-8) 400/ (4.5 VCC-8) 400/ (4.5 VCC-8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300
Limits Typ.
Max.
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is "1". Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is "0".
49
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (High-speed version)
Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Test conditions Unit Min. Typ. Max. tc(SCLK1)/2-30 ns tc(SCLK1)/2-30 ns 140 ns Fig. 32 -30 ns 30 ns 30 ns tc(SCLK2)/2-160 ns tc(SCLK2)/2-160 ns Fig. 33 200 ns 0 ns 30 ns 10 30 ns Fig. 32 10 30 ns
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT pin is excluded.
SWITCHING CHARACTERISTICS 2 (High-speed version)
Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions Min. tc(SCLK1)/2-50 tc(SCLK1)/2-50 -30 50 50 tc(SCLK2)/2-240 tc(SCLK2)/2-240 Fig. 33 0 20 20 50 50 50 400 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig. 32
350
Fig. 32
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT pin is excluded.
50
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (High-speed version)
Symbol tsu(ONW-) ____ th(-ONW) tsu(DB-) th(-DB) ____ __ tsu(ONW-RD) ____ ___ tsu(ONW-WR) __ ____ th(RD-ONW) ___ ____ th(WR-ONW) __ tsu(DB-RD) __ th(RD-DB)
____
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Min. -20 -20 50 0 -20 -20 50 0 25 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns
Parameter Before ONW input set up time _____ After ONW input hold time Before data bus set up time After data bus hold time ___ _____ Before RD ONW input set up time ___ _____ Before WR ONW input set up time ___ _____ After RD ONW input hold time ___ _____ After WR ONW input hold time ___ Before RD data bus set up time ___ After RD data bus hold time
_____
25
SWITCHING CHARACTERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) (High-speed version)
Symbol tc() twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) td(-DB) tv(-DB) Parameter Test conditions Min. tc(XIN)-10 tc(XIN)-10 2 2 16 5 20 5 16 5 15 35 40 Limits Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)-16 tc(XIN)-20 5 5 15 10 0 200 100 30 ns ns ns ns ns ns ns ns
clock cycle time clock "H" pulse width clock "L" pulse width After AD15-AD8 delay time After AD15-AD8 valid time After AD7-AD0 delay time After AD7-AD0 valid time SYNC delay time SYNC valid time After data bus delay time After data bus valid time ___ ___ RD pulse width, WR pulse width __ ___ ___ twL(RD) ___ RD pulse width, WR pulse width twL(WR) (when one-wait is valid) ___ __ td(AH-RD) After AD15-AD8 ___ delay time RD ___ td(AH-WR) After AD15-AD8 WR delay time ___ __ td(AL-RD) After AD7-AD0 ___ delay time RD ___ td(AL-WR) After AD7-AD0 WR delay time ___ __ tv(RD-AH) After ___ AD15-AD8 valid time RD ___ tv(WR-AH) After WR AD15-AD8 valid time ___ __ tv(RD-AL) After ___ AD7-AD0 valid time RD ___ tv(WR-AL) After WR AD7-AD0 valid time ___ ___ td(WR-DB) After WR data bus delay time ___ ___ tv(WR-DB) After WR data bus valid time _________ ___ _____ td(RESET-RESETOUT) RESETOUT output delay time (Note 1) _________ _____ tv(-RESET) RESETOUT output valid time (Note 1)
_________
30
10 tc(XIN)-10 Fig. 32 3tc(XIN)-10 tc(XIN)-35 tc(XIN)-40 2 2
Note 1: The______ RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
51
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 2.7 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) (High-speed version)
Symbol tsu(ONW-) ____ th(-ONW) tsu(DB-) th(-DB) ____ __ tsu(ONW-RD) ____ ___ tsu(ONW-WR) __ ____ th(RD-ONW) ___ ____ th(WR-ONW) __ tsu(DB-RD) __ th(RD-DB)
____
Parameter Before ONW input set up time _____ After ONW input hold time Before data bus set up time After data bus hold time ___ _____ Before RD ONW input set up time ___ _____ Before WR ONW input set up time ___ _____ After RD ONW input hold time ___ _____ After WR ONW input hold time ___ Before RD data bus set up time ___ After RD data bus hold time
_____
Min. -20 -20 120 0 -20 -20 120 0
Limits Typ.
Max.
Unit ns ns ns ns ns ns
60
60
ns ns
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (High-Speed Version) (VCC = 2.7 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol tc() Parameter Test conditions Min. tc(XIN)-20 tc(XIN)-20 5 5 40 10 50 10 40 10 30 100 100 clock cycle time clock "H" pulse width clock "L" pulse width AD15-AD8 delay time AD15-AD8 valid time AD7-AD0 delay time AD7-AD0 valid time SYNC delay time SYNC valid time Data bus delay time Data bus valid time ___ ___ RD pulse width, WR pulse width __ ___ ___ twL(RD) ___ RD pulse width, WR pulse width twL(WR) (when one-wait is valid) ___ __ td(AH-RD) After AD15-AD8 ___ delay time RD ___ td(AH-WR) After AD15-AD8 WR delay time ___ __ td(AL-RD) After AD7-AD0 ___ delay time RD ___ td(AL-WR) After AD7-AD0 WR delay time ___ __ tv(RD-AH) After ___ AD15-AD8 valid time RD ___ tv(WR-AH) After WR AD15-AD8 valid time ___ __ tv(RD-AL) After ___ AD7-AD0 valid time RD ___ tv(WR-AL) After WR AD7-AD0 valid time ___ ___ td(WR-DB) After WR data bus delay time ___ ___ tv(WR-DB) After WR data bus valid time _________ ___ _____ td(RESET-RESETOUT) RESETOUT output delay time (Note 1) _________ _____ tv(-RESET) RESETOUT output valid time (Note 1) twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) td(-DB) tv(-DB)
_________
Limits Typ. 2tc(XIN)
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
80
Fig. 32
10 tc(XIN)-20 3tc(XIN)-20 tc(XIN)-100 tc(XIN)-100 5 5 tc(XIN)-40 tc(XIN)-50 10 10 30 10 0 300 150 80
ns ns ns ns ns ns ns ns
Note 1: The______ RESETOUT output goes "H" in sync with the rise of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
1k
Measurement output pin 100pF
Measurement output pin 100pF
CMOS output
N-channel open-drain output
Fig. 32
Circuit for measuring output switching characteristics (1)
Fig. 33
Circuit for measuring output switching characteristics (2)
52
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGLAM (1) Timing Diagram
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2 VCC
CNTR0, CNTR1
0.8 VCC
tWH(INT)
tWL(INT) 0.2 VCC
INT0-INT4
0.8 VCC
tW(RESET)
RESET
0.2 VCC
0.8 VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2 VCC
XIN
0.8 VCC
tf
tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2 VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) 0.8 VCC
SCLK1 SCLK2
th(SCLK1-RXD), th(SCLK2-SIN2)
RXD SIN2
0.8 VCC 0.2 VCC td(SCLK1-TXD),td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2)
TXD SOUT2
53
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2)Timing Diagram in Memory Expansion Mode and Microprocessor Mode (a)
tC() tWH() tWL()
0.5 VCC
td(-AH)
tv(-AH)
0.5 VCC
AD15-AD8
td(-AL)
tv(-AL)
0.5 VCC
AD7-AD0
td(-SYNC)
tv(-SYNC)
SYNC
0.5 VCC
td(-WR)
tv(-WR)
RD,WR
tSU(ONW-)
0.5 VCC
th(-ONW)
ONW
0.8 VCC 0.2 VCC
tSU(DB-)
th(-DB)
DB0-DB7 (At CPU reading) DB0-DB7 (At CPU writing)
0.8 VCC 0.2 VCC
td(-DB)
0.5 VCC
tv(-DB)
(3)Timing Diagram in Microprocessor Mode
RESET
0.8 VCC 0.2 VCC
0.5 VCC
td(RESET- RESET OUT)
tv(- RESETOUT)
RESETOUT
0.5 VCC
54
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (b)
tWL(RD) tWL(WR)
RD,WR
td(AH-RD) td(AH-WR)
0.5 VCC
tv(RD-AH) tv(WR-AH)
AD15-AD8
0.5 VCC
td(AL-RD) td(AL-WR)
tv(RD-AL) tv(WR-AL)
AD7-AD0
0.5 VCC
tsu(ONW-RD) tsu(ONW-WR)
th(RD-ONW) th(WR-ONW)
ONW (At CPU reading) RD
0.8 VCC 0.2 VCC
tWL(RD)
0.5 VCC
tSU(DB-RD)
th(RD-DB)
DB0-DB7
0.8 VCC 0.2 VCC
(At CPU writing) WR
td(WR-DB)
0.5 VCC
tWL(WR)
tv(WR-DB)
0.5 VCC
DB0-DB7
55
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1996 MITSUBISHI ELECTRIC CORP. H-DF047-C KI-9609 New publication, effective Sep. 1996. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
3806GROUP DATA SHEET
Revision Description Rev. date 971128
(1/1)

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